This invention relates to manufacture of insulated-gate field effect transistors, and more particularly to short-channel transistors having heavily-doped source/drain regions with lightly-doped regions adjacent the channels.
A high-performance insulated gate field effect transistor using oxide side-wall spacer technology to provide lightly-doped source/drain in disclosed by Tsang et al in IEEE Journal of Solid-State Circuits, April 1982, p. 220. This structure is advantageous for short channel transistors as needed in VLSI devices such as 256K-bit memory chips, for example. Small geometry transistors introduce a variety of problems including short channel Vt effects, low breakdown voltage and hot carrier generation which produce substrate and gate currents. The oxide side-wall-spacer technology tends to avoid some of these effects by reducing the electric field at the drain end of the transistor. Problems are introduced in fabrication to these devices, however, due to the etching process for creating the sidewall spacer. Also, the implant used to close the gap beneath the sidewall spacer results in a doping level higher than desired and the junction is not graded to the extent desired. Further, phosphorous can be unintentionally introduced from the multi-level insulator, and this produces a junction ahead of the arsenic-doped junction because phosphorous diffuses faster. Alternatives to the Tsang et al process were disclosed by Takeda et al at p. 245 of Journal of Solid State Circuits, April 1982, but none of these was suitable for high-performance dynamic RAMs. Arsenic is needed for the N+ source/drain regions so that the sheet resistance will be low. However, the arsenic implant previously used for the gap-closing implant is not acceptable because of the steep junction grading. This steep grading results in high electric fields which enhance impact ionization and hence produce high substrate and gate currents. The prior configuration also gives high overlap capacitance.
It is the principal object of this invention to provide improved short-channel MOS transistors for VLSI semiconductor devices. Another object is to provide an improved transistor employing oxide sidewall spacer technology.